Cadence Design Systems (NASDAQ:CDNS) Chief Executive Officer Anirudh Devgan said the company is positioned for continued growth as artificial intelligence increases demand for chip design tools, intellectual property and system design capabilities.
Speaking at the BofA Global Technology Conference in a fireside chat with Bank of America analyst Vivek Arya, Devgan said Cadence has delivered “phenomenal growth” over the past five years, including about a 15% compound annual growth rate, despite mixed conditions across parts of the semiconductor market. He also said margins have improved and that Cadence “crossed rule of 60 this year.”
AI Seen as a Net Positive
Devgan pushed back on concerns that AI could disrupt Cadence’s core software business, calling AI “a net positive” for the company. He described Cadence as participating in both “design for AI” and “AI for design,” meaning its tools are used to build AI chips while AI is also applied to improve design productivity.
He said AI-driven productivity is necessary because customer workloads are increasing rapidly. Devgan cited conversations with customers who say each next-generation chip requires far more engineering effort, calling that “an unrealizable headcount curve” without AI assistance.
Devgan said AI agents used in complex chip design still need Cadence’s “ground truth tools,” such as verification and simulation products, rather than replacing them. He pointed to Nvidia’s recent Computex discussion of Cadence tools and said Cadence’s ChipStack technology can increase usage of products such as Jasper and Xcelium when generating and verifying RTL.
“The number of base tool usage is going up versus a non-agentic world,” Devgan said.
Design Activity Remains Strong
Devgan said design starts remain strong and are increasing, despite higher costs at the leading edge of semiconductor manufacturing. He said the value of advanced chips is high enough that foundry pricing dynamics have not reduced design activity.
He pointed to vertical integration by major technology and industrial companies as a driver of additional chip design work. Devgan cited Google as an example in data center AI and Xiaomi as an example in physical AI, noting that Xiaomi has its own cars, AI model and chips.
He also said traditional semiconductor segments, including analog and memory, have improved from weaker conditions. Devgan described the overall market environment as “much better than a year ago.”
Agentic Tools Create New Opportunity
Devgan said Cadence’s agentic products, including ChipStack, ViraStack and InnoStack, are intended to automate tasks that customers previously handled manually. He described those products as both a source of customer productivity and a potential expansion of Cadence’s addressable market.
Internally, Devgan said Cadence is applying agentic tools to its own IP development. He said the company has roughly 15,000 employees, including about 4,000 customer-facing application engineers and about 10,000 in research and development. Of the R&D staff, he said about 3,000 work in IP.
Devgan said he expects at least a 2x productivity improvement in the IP group, with a target of at least a 30% reduction in headcount per project and a 30% reduction in schedule for a given project. He said some customers are seeking 2x to 4x productivity improvements from agentic flows.
Devgan added that Cadence’s operating margin is about 44% to 45%, while incremental margin has been about 60%.
IP Strategy Focused on Key Areas
Discussing Cadence’s intellectual property business, Devgan said IP had not been his initial investment priority because the company first needed to strengthen its EDA business. He said that has changed as AI and chip disaggregation have made certain types of IP more valuable.
Devgan said Cadence is focused on five “star IPs”: DDR memory subsystems, PCIe, UCIe, HBM and SerDes. He said the company’s strategy is to focus on advanced-node IP and win with leading customers by offering best-in-class power, performance and area.
He also said Cadence’s IP R&D team has improved and is now “world-class,” which he described as a key reason the IP business is gaining momentum.
Physical AI Viewed as Longer-Term Driver
Devgan said he remains optimistic about physical AI, robotics and edge AI, though he described the timeline as “three to seven years.” He said companies already must begin designing chips for those markets if products are expected within that time frame.
He cited activity among automakers and technology companies, including Tesla, BYD, NIO, XPeng, Xiaomi, Rivian, ADI, NXP, Nvidia, Qualcomm and MediaTek. Devgan said Cadence wants to be prepared for physical AI while continuing to focus on current opportunities in data center AI and agentic design tools.
“The physical AI part is to make sure we don’t miss the next big thing while focusing on the current big thing,” Devgan said.
About Cadence Design Systems (NASDAQ:CDNS)
Cadence Design Systems, Inc (NASDAQ: CDNS) is a global provider of electronic design automation (EDA) software, hardware and intellectual property used to design and verify advanced semiconductor chips, systems-on-chip (SoCs), printed circuit boards (PCBs) and packaging. Headquartered in San Jose, California and founded in 1988, Cadence serves semiconductor companies, original equipment manufacturers and system designers across the globe, helping customers accelerate design cycles and manage the complexity of modern integrated systems.
The company’s offerings span software tools for digital, custom/analog and mixed-signal design, verification and signoff, as well as solutions for system-level modeling, thermal and signal integrity analysis, and PCB and package design.
